A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs

摘要

The use of non-binary weighted DACs with redundant DAC capacitor weights has been shown to provide significant speed improvements in SAR ADCs. The non-binary SAR algorithm has an in-built correction mechanism against bit decision errors caused by incomplete DAC settling by providing overlap ranges in the search space and allowing alternative bit decision paths for approximating a given input voltage. In this paper we propose to use overlap ranges not only for speed-improvement but also for providing immunity to noise in the least-significant bit decisions thereby improving ADC robustness in noisy environments. Furthermore, we propose a systematic approach to the design of the redundant SAR ADC by providing an algorithm for determining the weights of the capacitors in the DAC to obtain the required DAC settling time improvement as well as noise immunity in the last few bit decisions as compared to a binary weighted SAR ADC. A 10-bit SAR ADC designed using the above weight distribution algorithm shows a 4X improvement in bit cycle-time (200ps) and a 5.5 dB improvement in noise immunity over the binary SAR ADC using 180 nm CMOS technology.