A 12-lead ECG integrated circuit design with adjustable gain and bandwidth schemes

摘要

In this paper an integrated circuit design for 12-lead Electrocardiogram (ECG) measurement is proposed. This ECG capture circuit is designed having adjustable gain and bandwidth via externally digital control. In addition to a third-order high-pass filter (HPF) with 1 Hz lower 3-dB frequency and a third-order low-pass filter (LPF) with 150 Hz upper 3-dB frequency, a second-order notch filter (NF) for 60Hz power line noise rejection is also designed on the chip. Besides, a right-leg drive circuit (RLDC) is added to attenuate the common-mode noise. Simulated results of the proposed ECG capture circuit reveal gain of about 40~70dB spanned from 0.1 to 150 Hz range excepting a 60 Hz notch point with attenuation lower than -57.6dB. The power consumption is 30mW from ±0.6V supply voltage. The core area is 1.2*2.4mm^{2in TSMC CMOS 0.18-μm process.}