AES implementation for RFID Tags: The hardware and software approaches

摘要

This work presents two different implementations of 128-bit AES cryptography for RFID tags: hardware module and software program. The hardware AES module has been designed with 0.13 um CMOS technology at 1.5 V. The size of the module is 7229 equivalent gates, and the maximum throughput is 130 Mbps. The power consumption at 125 kHz is 6 uA, which meets specification for low-power RFID tags at low frequency. The software version is implemented on a custom 8-bit microcontroller. The program is written in assembly language with our proprietary instruction set. It can process AES encryption in 6,012 instructions, which takes 20,601 clock cycles, using 2 kBytes of instruction memory and 320 Bytes of data memory. It is targeted to use in high-frequency RFID applications.