Frequency synthesizer system implementation for digital radar

摘要

This paper presents the implementation of a frequency synthesizer based on a Phase Locked Loop (PLL) system for an architecture that aims to miniaturize a digital radar test bed previously implemented using discrete microwave components. The designed synthesizer was capable of providing three distinct frequencies of 800 MHz, 2.0 GHz, and 2.4 GHz to respective chips of a digital radar system while minimizing the number of components needed. The paper focuses on obtaining the three distinct frequencies from a single PLL and frequency divider circuits. The issues caused by the loading of chips are addressed, allowing the three frequencies to be fed to 18 different chips. The final result consists of a PLL connected to an integrated circuits of dividers to output the three frequencies.