首页> 外文会议>Symposium on Integrated circuits and system design;Annual symposium on Integrated circuits and system design;SBCCI >Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic
【24h】

Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic

机译:评估大容量内置电流传感器的故障范围,以了解组合和顺序逻辑中的软错误

获取原文

摘要

In this paper, we propose a new approach for using Built-in Current Sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition, the proposed BICS can inform if the upset has occurred in the PMOS or NMOS transistors, which can generate a more precise evaluation of the corrupted region. The proposed approach was validated by Spice simulation. The BICS and the case-studied circuits were designed in the 100nm CMOS technology. The bulk BIC sensor detects various shapes of current pulses generated due to charged particle strike. Results show that the proposed bulk BICS presents minor penalties for the design in terms of area, performance and power consumption and it has high detection sensitivity.
机译:在本文中,我们提出了一种使用内置电流传感器(BICS)的新方法,该方法不仅可以检测时序逻辑中的瞬态扰动,还可以检测组合电路中的瞬态扰动。在这种方法中,BICS连接在设计主体中以提高其灵敏度,以检测在带电粒子撞击期间可能出现的任何电流差异。此外,建议的BICS可以告知是否在PMOS或NMOS晶体管中发生了翻转,从而可以对损坏的区域进行更精确的评估。拟议的方法已通过Spice仿真进行了验证。 BICS和案例研究电路均采用100nm CMOS技术设计。大块BIC传感器检测由于带电粒子撞击而产生的各种形状的电流脉冲。结果表明,拟议的批量BICS在面积,性能和功耗方面对设计的影响较小,并且具有较高的检测灵敏度。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号