Modeling, simulation, and design methodology of the interconnectand packaging of an ultra-high speed source synchronous bus

摘要

In this paper, we describe the modeling, simulation and designmethodology of the interconnect and packaging for a 400 MHz L2 levelcache. Since the bus is source synchronous or “self timed”,the signal integrity, and hence the electrical performance of thepackage and board interconnects is a major limiter to the bus speed. Tothis end, we present circuit design techniques to alleviate packagingproblems such as the implementation of a dynamically controlled driverimpedance and edge rate. The timing equations for the source synchronousI/O bus are written in terms of the basic fundamental limitations of thesilicon, package, and board processes. The interconnect performancemodeling and simulation methodologies used to optimize these equationsare described