Squeezing more CPU performance out of a Cray-2 by vector blockscheduling

摘要

Compile-time scheduling of vector activities on the Cray 2 isstudied using a simplified model of the vector instruction stream. Anapproach based on experience with an array-processor microde schedulingby the authors is shown to be practical. It calls for a pass of loopscheduling followed by a pass of resource allocation. Actual benchmarksof the resulting code are shown, exhibiting speedups as large as 50%over the current CFT77 compiler. The results also give a novelperspective on vector chaining vs. nonchaining processor architectures