A novel digital chirp generator using a dual clock fieldprogrammable gate array architecture

摘要

The use of digital frequency synthesizers (FSs) to generate chirpsignals is discussed. Digital generation methods include: (a) waveformsynthesis by memory devices/digital processing devices, and (b) directdigital frequency synthesis (DDFS). The DDFS is usually programmed byeither a counter or a frequency accumulator (FA). The digitallygenerated chirp signal has a stepped frequency vs time characteristicwhich results in unwanted sidebands. Their level can be kept below thenoise level of the synthesizer by a proper choice of the frequency stepsize and its update rate. However, due to the digital nature of theDDFS, the tendency has become to use synthesizers with very finefrequency resolution and a frequency update rate equal to the operatingspeed of the synthesizer. To cover the HF frequency band, this requiresthe use of either ECL logic or GaAs logic which consume more power thanconventional TTL or fast CMOS and are more difficult to construct. Inaddition, FSs with very fine frequency resolution require a large sizeFA. Expressions for the sideband levels of the generated/demodulatedsignals are given. The increased complexity of the programmer does notresult in improved performance. A new architecture which uses a doubleaccumulator and a dual clock is proposed. This enables the use of TTL orCMOS logic for the FA which reduces the power consumptionoise. Also,the duration of the sweep signal can be controlled independently of theoutput frequency. A prototype dual clock chirp generator using on gatearrays is presented