This paper aims to make progress toward analyzing possible minimum power savings from removing the ICA processing block from an wireless EEG sensing unit. In general, removing the ICA processing block from an EEG sensing unit reduces power consumption; however, to evaluate the removal~，s effectiveness and determine possible minimum power savings, we analyzed a hardware implementation of EASI ICA. We designed a 6-input EASI ICA implementation using System Verilog based on an existing 2-input EASI ICA Verilog implementation. The EASI ICA algorithm has proven to be functional even after increasing the number of input component signals. Future research will involve simulating the power consumption of this ICA module and possibly loading the hardware design onto an FPGA to measure power consumption in the real world.
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