Design and Implementation of a Dual loop controller for a single-phase 5-level Cascaded H-Bridge Inverter with Reduced THD

摘要

This paper aims to design and implement a dual loop controller based single phase 5-level Cascaded H bridge inverter using carrier based level shifted pulse width modulation scheme. A cascaded H bridge inverter not only provides multiple output voltage levels for lesser Total Harmonic Distortion, but also provides modularity. The control strategy consists of two feedback loops for better response and stability. It comprises an inner current loop and an outer voltage loop. Both the loops are controlled by PR controllers The inner current loop is controlled by a non-ideal PR controller whereas the outer voltage loop is controlled by an ideal PR controller. Steady state performance of this type of controller is much better than the conventional PI based controller. Designing the controller, filter and implementation of the inverter is carried out in simulation Using MATLAB code and Simulink.