A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET

摘要

This paper describes a 4 × 112 Gb/s digital receiver targeting Long Reach (LR) channels. The discrete time front-end overcomes gain-BW limitations to provide 10+dB gain at 28GHz. A 56GS/s ADC then converts the signal to 6-b digital consuming only 195mW. The following DFE-FFE based digital equalizer is capable of compensating 36 dB loss achieving BER of 2e-5. Furthermore, TDC and ISI filter based low latency timing recovery meets jitter tolerance specs over a wide range of data rates (25Gb/s NRZ to 106.25Gb/s PAM-4). The overall receiver consumes 338mW with 3.18pJ/bit energy efficiency