Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture

摘要

The capacity and the energy consumption of the last-level cache (LLC) must be improved toward future microprocessors. This paper proposes an STT-RAM-based hybrid cache architecture (HCA) and its replacement policy, named the Fast Region First Used (FRFU) policy. The proposed HCA is composed of two types of STT-RAM devices with different characteristics to mitigate the disadvantages of non-volatile STT-RAM devices. The FRFU policy provides the better handling of the data blocks for the proposed HCA than the LRU policy. The evaluation results show that the proposed HCA and its policy can successfully reduce the energy consumption by 55% and improve the performance by 1% on average compared with a conventional SRAM LLC.