$(N+1)imes mathrm{V}_{mathrm{DD}}$ Gate-Voltage Boosting Circuit

摘要

This brief proposes an (N+1)×V_DD gate-voltage boosting circuit. The conventional gate-voltage boosting circuit generates an output-voltage swing of 0~2V_DD from the input-voltage swing of 0~V_DD. The proposed circuit simply expands the output-voltage swing of 0~(N+1)×V_DD by using N gate-voltage boosting stages. Each stage consists of a capacitor and three transistors and increases the swing voltage by V_DD, but its boosted voltage is lower than V_DD due to the parasitic capacitance. The proposed circuit was fabricated using a 65nm CMOS process. The measured output-voltage swings are 0~340mV, 0~495mV, and 0~658mV for the 2V_DD, 3V_DD, and 4V_DD gate-voltage boosting circuits, respectively, at V_DD=200mV. Their boost efficiency, which is the measured output over the ideal output (N×V_DD), are 86%, 83%, and 83%, respectively.