A FPGA Verification of Improvement Edge Detection using Separation and Buffer Line

摘要

This paper investigates the performance of an improved edge detection algorithm on an FPGA platform. The algorithm has three blocks: gray scale and Gaussian filter, separation and buffer line, Prewitt filter. Separation and buffer line method are needed to improve edge detection speed. Therefore, when converting to frames per second, the speed is improved to 183frames/s, which is faster than conventional method. A proposed algorithm was implemented using Matlab program and it is verified through a RTL-level simulation of ISE14.3.