20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC

摘要

IoT devices usually operate in random-sparse-event scenarios (Fig. 20.2.1). To avoid missing events, traditionally a periodic-wake-up frequency [1] must be orders of magnitude higher than the average event rate, wasting huge power. An emerging event-driven approach seeks to trigger a power-hungry highperformance system (HPS) using an ultra-low-power wake-up circuit. State-of-the-art wake-up chips with DSP-based and neural-network-based feature extraction consume 12nW [2], 1µW [3], and 142nW [4]. However, they can only respond to dedicated voice/acoustic signal of low bandwidth. Another wake-up chip with 2.2µW power [5] shows potential for general purpose use, however, the pattern recognition technology is complicated and power hungry for many IoT devices. Considering the cost, the versatile and continuously emerging IoT applications, and time-to-market, a general-purpose wake-up chip defined by software with ultra-low power is highly desired, but not yet reported.