17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word

摘要

Despite their superiority in silicon integration, ring-oscillator-based digital PLLs (RO-DPLLs) are seldom used for mobile transceivers because they have difficulty in meeting key requirements, such as low phase noise (PN) and high-frequency resolution. Due to the dilemma of setting the optimal bandwidth, considering the ΔΣM noise and the ring DCO poor PN, conventional ΔΣM-based fractional-N RO-DPLLs are limited in their ability to achieve low PN. To address this issue, the use of a digital-to-time-converter (DTC) to cancel the quantization noise (Q-noise) has become a general trend [1]. Figure 17.3.1 shows that, using a DTC that generates τDTC according to the control word of the DTC, DDCW, these DPLLs can have a wide bandwidth, thereby significantly suppressing the DCO PN. However, the problem is that any nonlinearity in the loop could cause a significant increase in fractional spurs. In practice, the DTC is the major source of this nonlinearity, so one solution is to improve its linearity by pre-distorting DDCW for its own characteristics, fDCW, [2], but this increases the design complexity. Another method is to use a successive requantizer (SR) as a quantizer (instead of a ΔΣM) [3]. The SR can mitigate fractional spurs despite the nonlinearity of the DTC, but the DTC must have a larger dynamic range than the ΔΣM with the same order.