A Novel Approach for FPGA Implementation of Register Exchange Based Viterbi Decoder and Re-Encoding based Node Synchronizer

摘要

This paper presents: (i) A novel method for VHDL implementation of register exchange based soft-hard decision Viterbi decoder in order to augment link margins available for “rover to lander” and “lander to orbiter” telemetry links and its performance evaluation and (ii) Re-encoding based node synchronizer. Register exchange method is faster and have low latency as compared to traceback method, but the main disadvantage of register exchange is that it needs large number of registers to store the decoded bits corresponding to each state in trellis. Using memory based implementation for path metric computation, survival state management and register exchange, have reduced the large number of registers requirement. Bit error rate performance evaluation of the implemented hard and soft decision decoding have been carried out by varying trellis depth and soft quantization bits. The performance and threshold evaluation for node synchronizer to decide “In-Sync”, “Out-Of-Sync” have been carried out.