Design and Implementation of Encoder and Decoder for Cyclic Redundancy Check

摘要

Cyclic Redundancy Check (CRC) is one of the most important method to detect the errors occurred during the transmission of any data. Errors are detected in communication due to internal and external factors. This paper presents an implementation and analysis of encoder and checker of CRC8 which takes 16-bits of input data to create 24-bits code-word and can detect errors up to 8-bits. The proposed design is functionally synthesized with VHDL and verified using Xilinx ISE 14.7 Software. The hardware implementation of this design is done on Xilinx Artix-7 FPGA board. Simulation based results are reported in this paper.