Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments

摘要

Verification of Field Programmable Gate Array (FPGA) designs is a challenging task which can be managed in different ways. By now, Universal Verification Methodology (UVM) is the de-facto standard for functional verification of Register Transfer Level (RTL) designs throughout all industry branches. Among others, UVM proposes to check for correct Device Under Test (DUT) behavior in an automated way, based on observing applied stimulus used to predict the expected DUT reaction. However, the prediction requires a DUT model whereas some DUT properties are complicated or even impossible to predict. Volatile registers are an example for this kind of problem. This paper introduces a way to incorporate volatile register comparisons inside the UVM environment alongside standard registers. This is done by utilizing System Verilog Assertions (SVA) which observe volatile registers to provide their values to the UVM environment directly at the time they are accessed.