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A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider

机译:基于重定时小数分频器的12 GHz全数字免校准FMCW信号发生器

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A 12-GHz all-digital calibration-free frequency-modulated continuous-wave (FMCW) signal generator is presented in this paper based on a retiming fractional frequency divider (FFD). Instead of modulating a multi-modulus divider (MMD) by a $DeltaSigma$ modulator, a fractional divider is utilized to release the narrow loop bandwidth limitation and achieve better phase noise without active noise cancellation techniques. Thus, the FMCW signal generator can achieve low root-mean-square (RMS) frequency error under a fast chirp slop. A calibration-free retiming FFD architecture which is not sensitive to process, voltage and temperature (PVT) variations is proposed to avoid complex and slow calibration process. Implemented in 40-nm CMOS, the generator consumes 33.8 mW power and 0.32 mm2 chip area. Measurement results show that the generator achieves 78 $mathrm{MHz}/mumathrm{s}$ maximum chirp slope and 6.0 kHz RMS frequency error when 300 MHz frequency is swept in 2 ms. The phase noise from 12 GHz carrier is -113.6 dBc/Hz at 1 MHz offset.
机译:本文提出了一种基于重定时分数分频器(FFD)的12 GHz全数字免校准调频连续波(FMCW)信号发生器。而不是通过 $ \ Delta \ Sigma $ < / tex> 调制器,分数分频器用于释放窄环路带宽限制,并获得更好的相位噪声,而无需有源噪声消除技术。因此,FMCW信号发生器可以在快速线性调频斜率下实现低均方根(RMS)频率误差。为了避免复杂且缓慢的校准过程,提出了一种对过程,电压和温度(PVT)变化不敏感的免校准重定时FFD体系结构。该发生器采用40 nm CMOS实施,功耗为33.8 mW,功耗为0.32 mm 2 芯片面积。测量结果表明,发电机达到了78 $ \ mathrm {MHz} / \ mu \ mathrm {s} $ 在2 ms内扫描300 MHz频率时,最大线性调频斜率和6.0 kHz RMS频率误差。在1 MHz偏移下,来自12 GHz载波的相位噪声为-113.6 dBc / Hz。

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