RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing

摘要

Light-weight software-based test (SBST) techniques are increasingly being used for testing of modern processors because of the ease of synthesis using evolutionary approaches, coverage for difficult to test faults, non-intrusive nature, low hardware overhead etc. However, the test synthesis time required by SBST is high. In this paper, an advancement SBST technique, termed as Rapid SBST (RSBST) is proposed that reduces the overall test synthesis time by reusing the simulation responses of existing test programs of identical observability. The test codes, developed using the evolutionary process, that produce similar fault simulation results are reused for the fault evaluation. We exploit this reusability to enhance the speed of the test synthesis. The efficacy of the proposed scheme is demonstrated on a 32-bit MIPS processor and on a minimal configuration of 7-stage SPARC V8 Leon3 soft processor. The test code generated achieves a fault coverage of 97.3% for the MIPS processor and 96.2% for the Leon3 soft processor. The test pattern generation time is 90 hours and 98 hours for these two processors, respectively. For the similar processors, traditional SBST requires 122 hours and 142 hours, respectively while providing a coverage of 93.9% and 92.9%. So it may be concluded that the proposed RSBST technique speeds up by a factor of 1.35 while maintaining the fault coverage above 96.2%.