A Low Latency Decoding Algorithm for Grouping Variable Nodes on TLC NAND Flash Devices

摘要

The intra-cell characteristics of TLC NAND Flash memory are analyzed based on the channel model employed in this paper. In order to solve the read latency and the reliability degradation, caused by LDPC soft decision decoding and by the increase of flash storage density, respectively, a dynamic block grouping approach is proposed to divide all variable nodes (VNs) into three sub-blocks. To exploit the reliability of the VNs within the three sub-blocks, different update operations are performed in order. Moreover, the decoding latency is reduced with fewer iterations for the VNs in the most reliable sub-block, at the same time, the priority for updating of the reliable sub-block and the timely processing of the VNs with low-information have more useful information transmitted in the iterative decoding process, resulting in the improved convergency speed. In quantity, our simulation results show that the proposed algorithm improves the convergency rate by about 28.6% and reduces the average number of iterations by around 27.7%, compared with the VNBP-MP algorithm without compromising the error correction performance on the TLC NAND Flash devices.