Socrates-D 2.0: A Low Power High Throughput Architecture for Deep Network Training

摘要

Specialized ultra-low power deep learning architectures with on-chip training capability can be useful in variety of applications that require adaptability. This paper presents such a processor design, Socrates-D 2.0, a multicore architecture for deep neural network based training and inference. The architecture consists of a set of processing cores, each with internal memories to store synaptic weights. Additionally, we present a method to map traditional deep learning networks to our multicore architecture and show that there is minimal impact in training accuracy. The system level area and power benefits of the specialized architecture are compared with the earlier generation of Socrates-D. Our experimental evaluations show that the proposed architecture can provide 1.25× area and 1.19× energy efficiency than the previous version of Socrates-D.