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A High-Speed Data Acquisition and Preprocessing Method for Wirelessly Supervising Train Braking System

机译:无线监控列车制动系统的高速数据采集与预处理方法

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In a real-time control system with large amounts of data, a high-speed and efficient collection and processing is the prerequisite for smooth operation. The braking system of train is a typical example. During the braking process of the train, it is necessary to deal with the real-time data from air brake valve, auxiliary air cylinder, air cylinder, brake shoe and relay valve transmitted by different carriages. Therefore, this paper designs a set of high-speed data acquisition and processing system based on FPGA for wirelessly supervising train-braking system. The parallel transmission between FPGA and ADC will greatly improve the speed of data collection. The data processing module is a custom fuzzy processing module, which reduces the negative impact from the imprecise braking-model and the model change. The wireless communication and memory module use two SRAM working alternately to improve communication efficiency. According to the characteristics of the system, this design programming with modular design method based on verilog HDL and we use the finite state machine as the control module. Finally, we performed RTL level function simulation and timing analysis.
机译:在具有大量数据的实时控制系统中,高速,高效的收集和处理是平稳运行的前提。火车的制动系统就是一个典型的例子。在列车制动过程中,有必要处理由不同车厢传输的空气制动阀,辅助气缸,气缸,制动蹄和继动阀的实时数据。因此,本文设计了一套基于FPGA的高速数据采集与处理系统,用于无线监控列车制动系统。 FPGA和ADC之间的并行传输将大大提高数据收集的速度。数据处理模块是自定义的模糊处理模块,可减少不精确的制动模型和模型更改带来的负面影响。无线通信和内存模块使用两个交替工作的SRAM来提高通信效率。根据系统的特点,本设计程序采用基于Verilog HDL的模块化设计方法,并以有限状态机为控制模块。最后,我们进行了RTL级功能仿真和时序分析。

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