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System-on-Chip Linux-based Platform for High-Performance Time-to-Digital Conversion

机译:基于片上系统的Linux平台,可实现高性能的时间数字转换

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This contribution presents a complete hardware, firmware and software platform for high-resolution time measurements. The implementation is into Programmable Logic and Processing System sections of a Xilinx System-on-Chip, hosted on a custom carrier board together with front-end circuits, communication interfaces (USB, Ethernet) and power resources. The platform is provided with a software for system configuration, management of output measures. The internal Block-Design IP-Core offers several parameters for customization purpose, also allowing a settable trade-off between saving of resources and performance, with time precision ranging from 12 ps r.m.s. to 50 ps r.m.s. and resolution from 1 ps to 100 ps, configurable number of channels (from 2 to 16) and a rate of measurements up to 45 MHz per channel. The area occupation per channel ranges from 256 SLICEs for a resource-saving configuration to 2048 SLICESs for optimizing performance. Additionally, the IP-Core has a very low Cross-Talk (<; 3 ps r.m.s.) and temperature drift (286 fs/°C in the 0 °C - 70 °C operating range). The system is modular, permitting the integration of custom user-made software or firmware modules both in the form of spatial and temporal computing algorithms.
机译:这一贡献为高分辨率时间测量提供了完整的硬件,固件和软件平台。该实现包含在Xilinx片上系统的“可编程逻辑和处理系统”部分中,该部分与前端电路,通信接口(USB,以太网)和电源一起托管在定制载板上。该平台配有用于系统配置,输出措施管理的软件。内部的Block-Design IP-Core提供了几个用于定制目的的参数,还允许在节省资源和性能之间进行可设置的折衷,时间精度为12 psr.m.s。至50 ps r.m.s.分辨率从1 ps到100 ps,通道数量可配置(从2到16),测量速率高达每通道45 MHz。每个通道的面积占用范围从256个SLICE(用于节省资源的配置)到2048 SLICE(用于优化性能)。此外,IP核的串扰(<; 3 ps r.m.s.)和温度漂移(0°C-70°C工作范围内为286 fs /°C)非常低。该系统是模块化的,允许以空间和时间计算算法的形式集成定制的用户制作的软件或固件模块。

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