The present paper shows the full design and implementation in VHDL code of the sequential least squares algorithm to obtain the coefficients of the memory polynomial model. This model was selected to perform the behavioral modeling of power amplifiers for RF. Two main parts make up the design: a memory polynomial model with unit coefficients block and a sequential least squares calculation block. The design allows the extraction of the coefficients by providing only an input and an output of the power amplifier and makes the model more accurate with each iteration, it works with complex values which makes it possible modeling the amplitude-amplitude and amplitude-phase curves in a single model. The implementation was made through the Stratix IV DSP-FPGA development board and tested using 65,536 samples from a power amplifier NXP 10W measured at 2 GHz, achieving, an NMSE of -19.6884 dB.
展开▼
机译：本文展示了VHDL代码的顺序最小二乘算法的完整设计和实现，以获取存储多项式模型的系数。选择该模型来执行RF功率放大器的行为建模。该设计由两个主要部分组成：具有单位系数块和顺序最小二乘法计算块的存储多项式模型。该设计允许通过仅提供功率放大器的输入和输出来提取系数，并使模型在每次迭代中都更加精确，并且可以处理复杂的值，从而可以对中的振幅-振幅和振幅-相位曲线进行建模。一个模型。该实施是通过Stratix IV DSP-FPGA开发板完成的，并使用来自功率放大器NXP 10W的65,536个样本进行了测试，该样本在2 GHz下测量，达到NMSE -19.6884 dB。
展开▼
