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A 50 Gb/s Serial Link Receiver With Inductive Peaking CTLE and 1-Tap Loop-Unrolled DFE in 22nm FDSOI CMOS

机译:具有电感峰值CTL的50 GB / S串行链路接收器和22nm FDSOI CMOS中的1分接环展开DFE

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A 50 Gb/s serial link receiver is proposed in this paper. This work presents a high bandwidth inductive peaking con-tinuous-time linear equalizer (CTLE) with conjugate complex output poles. A loop-unrolled tap1-embedded-in-sampler decision feedback equalizer (DFE) is introduced to alleviate timing constraint for the first tap. The proposed circuit is implemented in 22nm FDSOI CMOS with 0.9V voltage supply. Simulation result shows that this receiver can achieve 50 Gb/s data rate with 26mW power consumption for 20dB loss at 25GHz channel.
机译:本文提出了50 GB / s串行链路接收器。该工作介绍了具有共轭复制输出磁极的高带宽感应峰值连续时间线性均衡器(CTLE)。引入了一个循环展开的TAP1嵌入式取样器判定反馈均衡器(DFE)以缓解第一个抽头的时序约束。所提出的电路以0.9V电压电源的22nm FDSOI CMOS实现。仿真结果表明,该接收器可以实现50 GB / S的数据速率,在25GHz通道中具有26mW的电量为20dB损耗。

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