A 50 Gb/s Serial Link Receiver With Inductive Peaking CTLE and 1-Tap Loop-Unrolled DFE in 22nm FDSOI CMOS

摘要

A 50 Gb/s serial link receiver is proposed in this paper. This work presents a high bandwidth inductive peaking con-tinuous-time linear equalizer (CTLE) with conjugate complex output poles. A loop-unrolled tap1-embedded-in-sampler decision feedback equalizer (DFE) is introduced to alleviate timing constraint for the first tap. The proposed circuit is implemented in 22nm FDSOI CMOS with 0.9V voltage supply. Simulation result shows that this receiver can achieve 50 Gb/s data rate with 26mW power consumption for 20dB loss at 25GHz channel.