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A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

机译:采用16nm FinFET的0.45V亚兆瓦全数字PLL,用于蓝牙低功耗(BLE)调制和使用32.768kHz参考的瞬时通道跳变

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The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.
机译:短距离无线收发器(例如BLE)的频率合成的当前范例是使用数十MHz范围内的晶体振荡器(XO)作为频率参考(FREF)来锁相RF振荡器[1- 4]。这样可确保数十到数百kHz的足够宽的PLL带宽,以快速获取新通道并抑制RF振荡器的低频相位噪声(PN)。可以通过大幅降低数控振荡器(DCO)的闪烁PN来减轻后一种要求,从而允许在接收(RX)数据包期间冻结其调谐字更新,并在发送(TX)数据包期间进一步直接FM调制DCO [1]。 ]。但是,仍然需要全数字PLL(ADPLL)才能快速将DCO稳定到每个新通道。

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