Advanced Bayer demosaicing on FPGAs

摘要

Demosaicing is the process of interpolating the output from a single chip colour filter array sensor to form a full colour image. In hardware, the simplest algorithms: zero order hold and bilinear interpolation, are commonly used because of their simplicity and low resource requirements. State of the art algorithms are difficult to implement in hardware because of their complex access patterns. This paper explores the streamed implementation of a higher order interpolation filter, with a weighted median classifier. Although this comes at a cost of a factor of 10 increase in hardware resources, and a reduction in maximum pixel clock frequency by 30%, this state of the art algorithm gives considerably improved images of 11.2 dB in peak signal to noise ratio with a considerable reduction in interpolation artifacts. For real-time applications where image quality is critical, an implementation of such an advanced demosaicing algorithm on FPGA is essential.