High performance asynchronous bit-level parallel interface for board-to-board inter processor communication

摘要

This paper presents a bit-level parallel communication interface used for inter processor communication separated on different printed circuit boards. A high performance board-to-board communication interface is important in modern supercomputers and portable computers or gadgets with multiple screen displays. We propose a recalibrated transmitter and receiver soft IP cores to support asynchronous handshake communication interface. The valid signal can be delayed for a few cycle to guarantee the metastability of data signals. The tuning of the delay can be recalibrated and tested during pre-implementation step. The flexibility to tune a correct valid delay time, which is set as minimum as possible as far as the data integrity can be guaranteed, enables the operation the communicating devices at its maximum performance. The proposed technique has been simulated using HDL-level simulation and has shown its expected performance with four testing scenarios.