首页> 外文会议>IEEE Custom Integrated Circuits Conference >A 12-/14-bit, 4/2MSPS, 0.085mm SAR ADC in 65nm using novel residue boosting
【24h】

A 12-/14-bit, 4/2MSPS, 0.085mm SAR ADC in 65nm using novel residue boosting

机译:使用新颖的残留增强功能的65nm的12位/ 14位,4 / 2MSPS,0.085mm SAR ADC

获取原文

摘要

In this paper, a re-configurable 12/13/14-bit SAR ADC based on a 12-bit ADC core is presented. A novel residue-boosting algorithm is developed to increase the bit resolution of a SAR ADC up to 2 bits without significant additional area and power. In the 12-bit mode, the 65nm prototype shows both DNL and INL of about +/0.5 LSB at 4MSPS, and in 14-bit mode, DNL and INL are about +/1 LSB and +/2 LSB at 2MSPS. ENOB is 11.5 bit and 13 bit for 12-bit and 14-bit mode each. The area of the ADC is 0.085mm.
机译:本文提出了一种基于12位ADC内核的可重新配置的12/13/14位SAR ADC。开发了一种新颖的残差增强算法,可将SAR ADC的位分辨率提高到2位,而不会显着增加面积和功耗。在12位模式下,65nm原型在4MSPS时显示DNL和INL约为+ / 0.5 LSB,而在14位模式下,在2MSPS时DNL和INL约为+ / 1 LSB和+ / 2 LSB。对于12位和14位模式,ENOB分别为11.5位和13位。 ADC的面积为0.085mm。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号