Verification Methods for Secure and Reliable SoPC Systems

摘要

Verification takes on a much greater importance in secure and reliable System-on-Programmable-Chip (SoPC) systems. A set of verification methods, containing static analysis and configuration-level simulation, is implemented and applied to a typical SoPC system in this paper. Static analysis methods are illustrated in detail, such as Coding-Style analysis, Clocking-Domain Crossing (CDC) analysis, and static timing analysis (STA). The configuration-level simulation platform is built based on Verification Methodology Manual for SystemVerilog (VMM). The verification results indicate that design errors of timing and anti-protocols have been exactly checked out with high verification coverage. The proposed verification methods, possessing fine configurability, flexibility and high performance, can be reused in similar verification of other designs.