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29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

机译:29.2适用于100Gb / s相干网络的发送器和接收器,具有20nm CMOS集成的4×64GS / s 8b ADC和DAC

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At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad low-power DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For long-haul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for stressed channels. Double sampling also enables the DSP to implement more complicated equalization schemes and more flexible spectrum engineering at high frequency on the transmitter side. This paper reports the receiver and transmitter fully integrated in a 100G coherent DSP chip, using 4×64GS/s ADCs and DACs with 8b resolution, fabricated in a standard 20nm CMOS process.
机译:在100Gb / s或更高速率下,集成有高采样率数据转换器的基于CMOS DSP的收发器对于实现基于相干检测的相敏调制方案至关重要,该方案对于城域网和长途网络至关重要[1] 。为了支持双极化QPSK格式,需要四路低功耗DAC和ADC,并且必须在XI,XQ,YI和YQ通道之间保持精确的相位对准,以便在相干系统中传输和提取相位信息,如图29.2.1所示。对于100Gb / s的长距离传输,由于FEC开销,每个通道的波特率可以高达32Gb / s。此外,接收器通常需要以64GS / s的速度进行两次采样,以实现可靠的时钟数据恢复和压力通道的SNR改善。双采样还使DSP能够在发送器端的高频处实现更复杂的均衡方案和更灵活的频谱工程。本文报道了使用标准的20nm CMOS工艺制造的4×64GS / s ADC和8b分辨率的DAC,它们完全集成在100G相干DSP芯片中的接收器和发送器。

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