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Analysis of D-Q Small-Signal Impedance of Grid-Tied Inverters

机译:并网逆变器的D-Q小信号阻抗分析

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This paper analyzes the small-signal impedance ofthree-phase grid-tied inverters with feedback control and phaselockedloop (PLL) in the synchronous reference (d-q) frame. Theresult unveils an interesting and important feature of three-phasegrid-tied inverters – namely, that its q–q channel impedance behavesas a negative incremental resistor. Moreover, this papershows that this behavior is a consequence of grid synchronization,where the bandwidth of the PLL determines the frequencyrange of the resistor behavior, and the power rating of the inverterdetermines the magnitude of the resistor. Advanced PLL, current,and power control strategies do not change this feature. An exampleshows that under weak grid conditions, a change of the PLLbandwidth could lead the inverter system to unstable conditions asa result of this behavior. Harmonic resonance and instability issuescan be analyzed using the proposed impedance model. Simulationand experimental measurements verify the analysis.
机译:本文分析了小信号阻抗 具有反馈控制和锁相的三相并网逆变器 同步参考(d-q)帧中的环路(PLL)。这 结果揭示了三相的一个有趣且重要的特征 并网逆变器–即,其q-q通道阻抗行为 作为负增量电阻。此外,本文 表明此行为是网格同步的结果, PLL的带宽决定了频率 电阻行为的范围以及逆变器的额定功率 确定电阻的大小。先进的PLL,电流, 和电源控制策略不会更改此功能。一个例子 表明在弱电网条件下,PLL的变化 带宽可能导致逆变器系统处于不稳定状态,因为 这种行为的结果。谐波谐振和不稳定性问题 可以使用建议的阻抗模型进行分析。模拟 实验测量结果验证了分析结果。

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