Linearization Technique of the Power Stage in Open-Loop Class D amplifiers

摘要

An efficient method to linearize the switching (power) stage of open-loop class D amplifiers is presented. This technique has been successfully applied to an open-loop fully-digital PWM class D amplifier designed in a 40nm CMOS process leading to nearly 15dB improvement in the Total Harmonic Distortion (THD). Simulated open-loop class D amplifier performance resulted to 105dBA Signal-to-Noise Ratio (SNR), and 1W output power over 8 Ω with 90% power efficiency and 0.014% THD.