A robust design framework for stable digital peak current-mode control under uniform sampling

摘要

Fully digital current-mode control (DCMC) has become popular in high frequency applications, primarily because of using the uniform sampling rate for both the voltage and current loops. This requires a lower sampling analog-to-digital converter (ADC), in which the inductor-current iL is sampled once in every switching cycle and the ripple current is emulated in the digital domain. Thus, this remains an important concern about the selection of the emulated-current slope. Earlier approaches attempt to extract the actual slopes of iL either using model predictive algorithms or using online computation by considering a few extra current samples. These methods are highly sensitive to system parameters and increase computational complexity. Moreover, this paper reports that even if accurate slope information is available, the uniform voltage-loop sampling often leads to sub-harmonic instability, even with the duty ratio D <; 0.5. Using discrete-time models, design methods show that the required stabilizing slope is different from the actual current slope, and the slope magnitude needs to be increased for a higher controller gain. This provides a robust design framework to devise a stable DCMC technique for fast recovery, without attempting to find the actual slope information. A buck converter prototype is made and the proposed controller is implemented using an FPGA device.