Investigation on FPGA based passive anti-islanding protection schemes for grid interfaced Distributed Generation system

摘要

Small-scale distributed energy systems possess the potential to meet local demand of power as well as feed the excess power to the grid. In such grid-tied systems, it is necessary to ensure the reliable tripping of grid-interfaced inverters whenever the grid is unintentionally disconnected. As such, anti-islanding protection schemes are crucial for grid-interfaced Distributed Generation (DG) systems which assure the safety of critical loads, devices and personnel. This paper evaluates the implementation of various FPGA based passive anti-islanding protection schemes and their comparative performance. The synchronization of the DG inverter with the grid is ensured with a Moving Average Filter based Phase Locked Loop (MAF-PLL). The filter also aids for providing an input to the Over/Under Frequency and the Rate of Change of Frequency (ROCOF) protection techniques that has been employed for protection against events of islanding in the DG system. The dc-link capacitor voltage is a reflection of the active power exchange at the Point of Common Coupling (PCC) and hence any mismatch at the PCC causes the dc-link voltage to fluctuate. An over and under voltage protection scheme at the PCC has also been used. The schemes are tested in simulation as well as hardware co-simulation environment to validate their functioning.