Power divider with tunable positive and negative group delays using parasitic compensated PIN diode

摘要

This paper presents a design of power divider with tunable positive and negative group delays. The positive group delay can be obtained between paths 2 and 1 whereas negative group delay (NGD) between paths 3 and 1. The NGD is controlled by varying bias voltage of parasitic compensated PIN diodes. For experimental verification, power divider was designed and fabricated at center frequency of 2.14 GHz. Measurement results had a good agreement with simulation results.