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A real-time circuit topology for battery impedance monitoring

机译:电池阻抗监控的实时电路拓扑

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All batteries suffer from irreversible electrochemical changes as a result of their continuous operation. Deep depths of discharge and/or high discharge currents will inherently result in a reduction of performance over time. To track a battery lifetime, or state of health (SoH) requires an extension from the common internal resistance model and must be regularly assessed. To track SoH, an intelligent battery management system can be deployed to track the drift in usable capacity, but without a minimal impedance model, the impulse response and runtime cannot be accurately depicted. Electrochemical impedance spectroscopy (EIS) has proved to be an effective tool to extract the signature equivalent circuit associated with a single battery module or cell. Unfortunately, implementation at low cost has remained a challenge. In this paper, the circuit topology for a stand-alone EIS measurement board is proposed in an effort to reduce cost and complexity. The challenges and design considerations in developing a real-time EIS board is discussed. The circuit topology is then verified through a simulation environment under low (1 Hz), medium (1 kHz), and high frequency (100 kHz) test cases.
机译:由于它们的连续操作,所有电池患有不可逆转的电化学变化。深度放电和/或高放电电流将固有地导致随时间的性能降低。为了跟踪电池寿命,或健康状态(SOH)需要延伸来自常见的内部电阻模型,必须定期评估。要跟踪SOH,可以部署智能电池管理系统以跟踪可用容量的漂移,但没有最小的阻抗模型,不能准确地描绘脉冲响应和运行时。电化学阻抗光谱(EIS)已被证明是提取与单个电池模块或单元相关联的签名等效电路的有效工具。不幸的是,低成本实施仍然是挑战。本文提出了一种独立EIS测量板的电路拓扑,以减少成本和复杂性。讨论了在开发实时EIS板上的挑战和设计考虑。然后通过低(1Hz),中(1 kHz)和高频(100 kHz)测试用例的仿真环境来验证电路拓扑。

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