Hardware-efficient implementation of WFQ algorithm on NetFPGA-based OpenFlow switch

摘要

The development of network services makes their requirements for bandwidth become higher and more various, which leads to difficulty in Quality of Service (QoS) guarantee. In this paper, an OpenFlow switch featuring Weighted Fair Queuing (WFQ) algorithm is proposed. The system is implemented into NetFPGA 1G board which utilizes Xilinx Virtex II Pro 50 technology. The results have shown that our circuit can deliver adequate level of QoS at a throughput of 8 Gbps in its current implementation. Due to the flexibility of the design, the WFQ circuit can be targeted for later technologies in order to provide higher throughput.