Creating Fastest Self timing Reference Path for High Speed Memory Designs

摘要

Portable mobile systems are usually not only power efficient but quite speed critical too. Mobile SoC designers tend to increase voltage of operation to aim for higher speeds, but as RC parasitic tracking delays used in self-timing paths for memory designs don't scale as good as logic does, it results in more than required read/write windows and poses as gating factor for high speed systems. Thus, in an attempt to appropriately scale frequency with voltage for memories, it's important to create a fastest self-timing loop in design to give required timing boost without compromising on robustness of design even as continue to support memory instances of different sizes. In this paper, we present a method to create fastest reference tracking path while striking balance between RC parasitic's and logic delays, which results in scaling up speed with higher VDDs. Compared with classical replica self-timing techniques, our proposed solution gives 10-25% gain in speed for corner memory instances.