Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist

摘要

Three???dimensional integrated circuits (3D ICs) suffer from new manufacturing defects (t=0) and latent defects (t=0), which pose great threats on the yield and reliability of 3D ICs. The stack yield of 3D ICs, on the one hand, is enhanced by pre-bond test that can prevent bad dies from being stacked. However, the pre???bond test inevitably incurs additional test cost. We therefore propose test architecture design and optimization for 3D System???on???chips that can dramatically reduce the cost of both pre???bond and post??? bond tests. With this test architecture, two of the biggest test challenges for 3D ICs ??? the limited number of pre???bond test???pins, and the inherent weakness of thermal dissipation during post???bond test ??? are addressed by a novel test???wire sharing scheme, and a sophisticated test session scheduling method, respectively. On the other hand, the stack yield of 3D stacked memory is further improved by our inter???die spare???sharing technique and the die???matching algorithms, in which we explore the opportunity of salvation for bad dies in the stack and achieve 30% yield gain with moderate spares. In order to improve the assembly yield in TSV fabrication process, we develop a fault model considering TSV coupling effect that has not been carefully investigated before. It leads our attention to a unique phenomenon, i.e., the faulty TSVs can be clustered. Thus, we propose a novel TSV redundancy architecture, composed of a light???weight switch design and two effective and efficient repair algorithms. Experimental results show that they have much higher repair rate than the existing solutions w.t. or w.o clustered TSV faults. We extend this TSV redundancy architecture to address two critical challenges: catastrophic TSV failure with extremely clustered TSV faults; circuit timing error that occurs in the runtime induced by the latent TSV defects. These works provide a systematic way to improve the yield and reliability for 3D ICs, which is o- significance impact, as a percentage increase of the yield means millions of dollars.