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An energy-efficient level shifter for low-power applications

机译:用于低功率应用的高能效电平转换器

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One effective way to reduce the power consumption of biomedical implantable devices is to employ different supply voltages for different parts of the system depending on the processing speed of each part. This, however, necessitates the use of voltage level converters. This paper presents a power-efficient voltage level-shifting architecture that is capable of converting low levels of input voltages (even sub-threshold levels) to high levels of output voltages. In order to reduce the transition time of the output signal and consequently power consumption, the proposed circuit utilizes a diode-connected transistor to reduce the swing of the critical node. Moreover, the pull-down network is also improved. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the target design of input low supply voltage of 0.4 V and high supply voltage of 1.8 V, the level-shifter has a propagation delay of 31ns, a static power dissipation of 1.16nW, and a power dissipation of 0.68μW for a 1-MHz input signal.
机译:减少生物医学可植入装置的功率消耗的一种有效方法是根据每个部分的处理速度为系统的不同部分采用不同的电源电压。但是,这需要使用电压电平转换器。本文提出了一种高功率效率的电压电平转换架构,该架构能够将低电平的输入电压(甚至是亚阈值电平)转换为高电平的输出电压。为了减少输出信号的转换时间并因此减少功耗,所提出的电路利用二极管连接的晶体管来减少关键节点的摆幅。此外,下拉网络也得到了改善。该结构在0.18μmCMOS技术中的布局后仿真结果表明,在输入低电源电压为0.4 V,高电源电压为1.8 V的目标设计下,电平转换器的传播延迟为31ns,静态功耗为1.16nW,1 MHz输入信号的功耗为0.68μW。

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