14.7 A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation

摘要

Complex SoCs in scaled CMOS processes integrate a large variety of digital, SRAM and noise-sensitive mixed-signal/analog circuit blocks such as PLLs, wireline/wireless/RF transceivers, sensor front-ends, etc. The on-die low-dropout regulators (LDO) used for fine-grain DVFS of digital and memory blocks must respond fast to large load transients to minimize voltage droops/overshoots without using large decoupling caps, while minimizing power overheads over a wide operating range. The noise-sensitive analog circuits, on the other hand, need LDOs that provide sufficiently high power supply rejection (PSR) and minimal output voltage ripple, while maximizing current efficiency. Fast and scalable digital (DLDO) [1], analog-assisted digital (AA-DLDO) [2]-[3] and hybrid (HLDO) [4] analog-digital LDOs targeted for digital and memory blocks, as well as high-PSRR analog LDOs (ALDO) [5] optimized specifically for analog circuits have been recently reported.