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8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications

机译:8.1适用于WSN应用的65nm CMOS的80nW保留11.7pJ /周期的活动亚阈值ARM Cortex-M0 +子系统

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The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction.
机译:广泛预期物联网将包含数十亿个连接的设备,其中许多将是无线传感器节点(WSN)。这带来的挑战之一是能源效率,因为定期更换数十亿个电池将被证明具有成本高昂的优势。节点成本是另一个问题,它将需要更大的集成度。易于开发软件也必须是硬件设计人员的首要任务。针对上述所有问题,本文提出了一种在低泄漏65nm CMOS中实现的11.7pJ /周期亚阈值WSN处理子系统,该系统可从250mV的850nW有功功率扩展到900mV的66MHz,具有完全集成的82%峰值效率电压稳压器,用于直接电池操作,并支持80nW CPU和RAM状态保持功率门控,以减少SW透明泄漏。

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