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PEEC-based solver acceleration using reluctance method and low rank compression technique

机译:基于磁阻法和低秩压缩技术的基于PEEC的求解器加速

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This paper presents a low rank compression technique which is used together with reluctance method and Schur complement to accelerate the performance of a PEEC-based solver. The system of linear equations which is achieved from the PEEC method is normally dense, therefore the coefficient matrix (MNA matrix) is sparsified using reluctance technique, and then Schur complement is applied on the MNA matrix which consists of separable blocks in order to form a new equation called Schur equation which is smaller in size than the original equation and hence it will be easier to be solved. Moreover, low rank compression is applied to compress the Schur matrix which will improve mostly the memory usage as well as solution time. Numerical results are demonstrated and discussed which are based on simulation of bus bars used in power frequency converters. The results show significant improvement in the performance while the overall error of the solution is kept to be around 10% when the reluctance matrix is sparsified up to 98%. However, due to the limitations of the proposed method, frequencies close to dc are not covered in this work.
机译:本文提出了一种低秩压缩技术,该技术与磁阻方法和Schur补语结合使用,可加快基于PEEC的求解器的性能。通过PEEC方法获得的线性方程组通常是稠密的,因此使用磁阻技术对系数矩阵(MNA矩阵)进行稀疏化,然后将Schur补码应用于由可分离块组成的MNA矩阵以形成新的方程式称为Schur方程,其大小比原始方程式小,因此更易于求解。此外,采用低秩压缩来压缩Schur矩阵,这将大大改善内存使用率和求解时间。基于在功率变频器中使用的母线的仿真,对数值结果进行了演示和讨论。结果表明,当磁阻矩阵稀疏化至98%时,解决方案的总误差保持在10%左右,性能得到了显着改善。但是,由于所提出方法的局限性,本工作未涵盖接近直流的频率。

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