Implementation of dynamic element matching DAC and its use for noise cancellation in ΔΣ fractional-N PLL

摘要

This paper shows the design of a 12 bit dynamic element matching (DEM) DACs which eliminates pulse shape, timing, and amplitude errors arising from component mismatches as sources of non-linear distortion in high resolution DACs. This has been proved through analytical and simulation results in 0.18 μm standard CMOS process. A set of sufficient conditions of the DEM encoder that ensure this effect, and a specific segmented DEM encoder that satisfies the sufficient conditions are presented here. Unlike the most previously published fully randomized DEM encoders, the complexity of this design does not grow exponentially with the number of bits of DAC resolution. Part of this DEM DAC may be included in noise cancellation circuit in ΣΔ fractional-N PLL. Analytical results are demonstrated with simulation results. Additionally, this paper provides the explanation of noise cancellation in ΣΔ fractional-N PLL and power dissipation versus circuit complexity trade off.