A low complexity floating-point complex multiplier with a three-term dot-product unit

摘要

In this paper, we propose a new design for a low complexity floating-point complex multiplier for DSP applications. The design uses a three-term dot-product unit that reduces the overlapped portion found in a previous two-term fused dot-product unit. Comparisons with a primitive fused adder-subtract unit, a dot-product unit and combinations of these primitive units have also been performed. The synthesis results using a 45-nm standard-cell library shows a 16% reduction in area and a 6% reduction in power consumption as compared to a previous complex multiplier using two fused dot-product units.