Hamming codes; SRAM chips; cyclic redundancy check codes; error detection; fault location; fault tolerant computing; field programmable gate arrays; logic design; radiation hardening (electronics); CRB; CRC method; DWC-CED technique; Hamming method; ISim; RE-computing with shifted operand method; RESO Method; SEC; SEU; SRAM-based FPGA; TMR; VHDL language; configuration memory; fault detection system architecture; fault free processor; fault location detection; fault tolerant configuration engine; faulty core recovery; frame based reconfiguration; integrated soft core processors; lockstep scheme; picoblaze core; radiation-induced temporary faults; single bit error detection; single-event upsets; soft error tolerance technique design; static memory element logic states; triple modular redundancy; xilinx ISE 13.2; Circuit faults; Field programmable gate arrays; Logic gates; CED; DWC; FPGA; PicoBlaze; SRAM; Soft errors; TMR; fault;
机译:基于可靠SRAM的FPGA中软核处理器的软件容错技术设计和分析
机译:软误差缓解技术对基于SRAM的FPGA leon3软处理器
机译:基于FPGA的设计的软错误率建模和缓解的分析技术
机译:基于FPGA的软核处理器软误差公差技术设计
机译:基于SRAM的FPGA中实现的软核处理器的硬件和软件容错
机译:基于FPGA和软核处理器的基于标记的实时视觉传感器
机译:软误差缓解技术对基于SRAM的FPGA leon3软处理器