Direct measurement of ingress and egress latency on 1000Base-T Gigabit Ethernet links

摘要

Any error in a physical layer's asymmetry corrections for egress and ingress latency can result in uncorrectable timing error. These asymmetries increase the timing inaccuracy of any PTP system. A technique to directly measure the ingress and egress latencies of a 1000Base-T Gigabit Ethernet physical layer is presented.